Lifetime estimation of thin-film transistors in organic emitting diode display panels with compensation.

Oxide semiconductor thin-film transistors (TFTs) are used in the pixel array and gate driver circuits of organic light emitting diode (OLED) display panels. Long-term reliability characteristics of the TFTs are a barometer of the lifetime of OLED display panels. The long-term reliability of the driver TFTs is evaluated in a short time under high voltages and high temperature for an accelerated degradation test. If reliability parameters from the power law or stretched-exponential functions are the same for individual devices and devices in an operating panel, the lifetime of the panel can be accurately estimated. However, since compensation circuits are designed into operating panels, an environmental discrepancy exists between the accelerated test of single devices and the operation of devices in the panel. Herein, we propose a novel compensation stretched-exponential function (CSEF) model which captures the effect of the threshold voltage compensation circuit in the panel. The CSEF model not only bridges the discrepancy between individual devices and panel devices, but also provides a method to accurately and efficiently estimate the long-term lifetime of all display panels that utilize compensation circuits.

Deterministic field-free voltage-induced magnetization switching with self-regulated precession for low-power memory.

Spintronic devices are regarded as a promising solution for future computing and memory technologies. They are non-volatile, resilient to radiation, and compatible with the CMOS back-end process. However, the major drawbacks of modern current-driven spintronic devices are the long switching delay and relatively high power consumption. Recent progress in magnetoelectronics, particularly in voltage-controlled magnetism reveals a possible solution. Voltage-controlled magnetic anisotropy (VCMA) allows the manipulation of interface-mediated perpendicular anisotropy energy. However, most VCMA-based switching methods require pre-read operation, precise pulse-width control and have high write error rate. This study proposes a novel deterministic self-regulated precessional ferromagnet switching method, which overcomes these issues. In the discussed method, energy symmetry is broken by a dependence of MTJ resistance on the angle between magnetization vectors of free and pinned layers. Hence, the method does not require an external magnetic field and large electric current. The proposed method is verified through micromagnetic simulations and benchmarked with other methods typically reported in the literature. We report the write error rate is significantly improved compared to other VCMA switching methods. Moreover, the mean energy consumption is as low as 38.22 fJ and the mean switching delay is 3.77 ns.

Device-Algorithm Co-Optimization for an On-Chip Trainable Capacitor-Based Synaptic Device with IGZO TFT and Retention-Centric Tiki-Taka Algorithm.

Analog in-memory computing synaptic devices are widely studied for efficient implementation of deep learning. However, synaptic devices based on resistive memory have difficulties implementing on-chip training due to the lack of means to control the amount of resistance change and large device variations. To overcome these shortcomings, silicon complementary metal-oxide semiconductor (Si-CMOS) and capacitor-based charge storage synapses are proposed, but it is difficult to obtain sufficient retention time due to Si-CMOS leakage currents, resulting in a deterioration of training accuracy. Here, a novel 6T1C synaptic device using only n-type indium gaIlium zinc oxide thin film transistor (IGZO TFT) with low leakage current and a capacitor is proposed, allowing not only linear and symmetric weight update but also sufficient retention time and parallel on-chip training operations. In addition, an efficient and realistic training algorithm to compensate for any remaining device non-idealities such as drifting references and long-term retention loss is proposed, demonstrating the importance of device-algorithm co-optimization.

Lateral double magnetic tunnel junction device with orthogonal polarizer for high-performance magnetoresistive memory.

Magnetic tunnel junction (MTJ)-based memory devices have larger switching delay and energy consumption, compared to cache or dynamic random access memory. In order to broaden the applications of the magnetoresistive random access memory, reducing the switching time and energy consumption of the MTJ is required. Here, a novel lateral double MTJ with an orthogonal polarizer is proposed. The proposed device consists of three ferromagnetic regions: the first pinned region (PR1) with perpendicular magnetic anisotropy (PMA), a free region (FR) with PMA, and the second pinned region (PR2) with in-plane magnetic anisotropy (IMA). PR1 and PR2 are placed on top of the oxide barrier, which separates them from the FR, comprising a lateral double MTJ structure. The current pulse through PR2 helps to perturb the magnetization of the FR. Since the angle between PR2 and FR is 90°, the initial torque increases significantly, decreasing switching delay by 4.02 times and energy-delay product by 7.23 times. It is also shown, that the area of the access transistor can be reduced by approximately 10%, while maintaining the same energy-delay product and reducing gate RC delay.

Cation Composition-Dependent Device Performance and Positive Bias Instability of Self-Aligned Oxide Semiconductor Thin-Film Transistors: Including Oxygen and Hydrogen Effect.

Amorphous oxide semiconductor transistors control the illuminance of pixels in an ecosystem of displays from large-screen TVs to wearable devices. To satisfy application-specific requirements, oxide semiconductor transistors of various cation compositions have been explored. However, a comprehensive study has not been carried out where the influence of cation composition, oxygen, and hydrogen on device characteristics and stability is systematically quantified, using commercial-grade process technology. In this study, we fabricate self-aligned top-gate structure thin-film transistors with three oxide semiconductor materials, InGaZnO (In/Ga/Zn = 1:1:1), In-rich InGaZnO, and InZnO, having mobility values of 10, 27, and 40 cm2/V·s, respectively. Combinations of varied amounts of oxygen and hydrogen are incorporated into each transistor by controlling the fabrication process to study the effect of these gaseous elements on the physical nature of the channel material. Electrons can be captured by peroxy linkage (O22-) or undercoordinated In (In* to become In+), which are manifested in the extracted subgap density-of-states profile and first-principles calculations. Energy difference between electron-trapped In+ and O22- σ* is the smallest for IGZO, and In+-O22- annihilation occurs by electron excitation from the subgap In+ state to the O22- σ*. Furthermore, characteristic time constants during positive bias stress and recovery reveal the various microscopic physical phenomena within the transistor structure between different cation compositions.

Artificial van der Waals hybrid synapse and its application to acoustic pattern recognition.

Brain-inspired parallel computing, which is typically performed using a hardware neural-network platform consisting of numerous artificial synapses, is a promising technology for effectively handling large amounts of informational data. However, the reported nonlinear and asymmetric conductance-update characteristics of artificial synapses prevent a hardware neural-network from delivering the same high-level training and inference accuracies as those delivered by a software neural-network. Here, we developed an artificial van-der-Waals hybrid synapse that features linear and symmetric conductance-update characteristics. Tungsten diselenide and molybdenum disulfide channels were used selectively to potentiate and depress conductance. Subsequently, via training and inference simulation, we demonstrated the feasibility of our hybrid synapse toward a hardware neural-network and also delivered high recognition rates that were comparable to those delivered using a software neural-network. This simulation involving the use of acoustic patterns was performed with a neural network that was theoretically formed with the characteristics of the hybrid synapses.

Organic/Inorganic Hybrid Buffer in InGaZnO Transistors under Repetitive Bending Stress for High Electrical and Mechanical Stability.

We investigated the influence of the multilayered hybrid buffer consisting of Al2O3/PA (polyacrylic) organic layer/Al2O3 on the electrical and mechanical properties of amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs). The multilayered organic/inorganic hybrid buffer has multiple beneficial effects on the flexible TFTs under repetitive bending stress. First, compared to the PA or Al2O3 single-layered buffer, the multilayered hybrid buffer showed an improved WVTR value of 1.1 × 10-4 g/m2 day. Even after 40,000 bending cycles, the WVTR value of the hybrid buffer increased only by 17%, while the WVTR value of the Al2O3 layer doubled after cyclical bending stress. We also confirmed that the hybrid buffer has advantages in mechanical durability of the TFT layers because of the change in the position of the neutral plane and the strain reduction effect by the PA organic layer. When we fabricate a top-gate a-IGZO TFT with the hybrid buffer layer (HB TFT), the device shows Vth = 0.74 V, µFE = 14.4 cm2/V·s, a subthreshold slope of 0.27 V/dec, and hysteresis of 0.21 V, which are superior to that of TFTs fabricated on an Al2O3 single-layer buffer (IB TFT). From the X-ray photoelectron spectroscopy and elastic recoil detection analysis, the difference in the electrical performance of TFTs could be explained by hydrogen-related molecules. After annealing at 270 °C, the amounts of hydrogen found in the a-IGZO layer for the IB, HB, and OB TFTs were 3.57 × 1021, 5.77 × 1021, and 7.34 × 1021 atoms/cm3, respectively. A top-gate bottom-contact structured a-IGZO TFT fabricated on the PA layer (OB TFT) showed a gate dielectric breakdown because of excessively high hydrogen content and high nonbonding oxygen content. On the other hand, HB TFTs showed better positive bias stability because of the higher hydrogen concentration, as hydrogen (when not excessive) is beneficial in passivating electron traps. Finally, we conducted 60,000 repetitive bending cycles on IB TFTs and HB TFTs with various bending radii down to 1.5 mm. The HB TFT shows improved mechanical durability and exhibits less electrical degradation during and after repetitive bending stress, compared to the IB TFT.

Artificial optic-neural synapse for colored and color-mixed pattern recognition.

The priority of synaptic device researches has been given to prove the device potential for the emulation of synaptic dynamics and not to functionalize further synaptic devices for more complex learning. Here, we demonstrate an optic-neural synaptic device by implementing synaptic and optical-sensing functions together on h-BN/WSe2 heterostructure. This device mimics the colored and color-mixed pattern recognition capabilities of the human vision system when arranged in an optic-neural network. Our synaptic device demonstrates a close to linear weight update trajectory while providing a large number of stable conduction states with less than 1% variation per state. The device operates with low voltage spikes of 0.3 V and consumes only 66 fJ per spike. This consequently facilitates the demonstration of accurate and energy efficient colored and color-mixed pattern recognition. The work will be an important step toward neural networks that comprise neural sensing and training functions for more complex pattern recognition.

Author Correction: The Mobility Enhancement of Indium Gallium Zinc Oxide Transistors via Low-temperature Crystallization using a Tantalum Catalytic Layer.

A correction to this article has been published and is linked from the HTML and PDF versions of this paper. The error has not been fixed in the paper.

The Mobility Enhancement of Indium Gallium Zinc Oxide Transistors via Low-temperature Crystallization using a Tantalum Catalytic Layer.

High-mobility indium gallium zinc oxide (IGZO) thin-film transistors (TFTs) are achieved through low-temperature crystallization enabled via a reaction with a transition metal catalytic layer. For conventional amorphous IGZO TFTs, the active layer crystallizes at thermal annealing temperatures of 600 °C or higher, which is not suitable for displays using a glass substrate. The crystallization temperature is reduced when in contact with a Ta layer, where partial crystallization at the IGZO back-channel occurs with annealing at 300 °C, while complete crystallization of the active layer occurs at 400 °C. The field-effect mobility is significantly boosted to 54.0 cm2/V·s for the IGZO device with a metal-induced polycrystalline channel formed at 300 °C compared to 18.1 cm2/V·s for an amorphous IGZO TFT without a catalytic layer. This work proposes a facile and effective route to enhance device performance by crystallizing the IGZO layer with standard annealing temperatures, without the introduction of expensive laser irradiation processes.

Flexible and High-Performance Amorphous Indium Zinc Oxide Thin-Film Transistor Using Low-Temperature Atomic Layer Deposition.

Amorphous indium zinc oxide (IZO) thin films were deposited at different temperatures, by atomic layer deposition (ALD) using [1,1,1-trimethyl-N-(trimethylsilyl)silanaminato]indium (INCA-1) as the indium precursor, diethlzinc (DEZ) as the zinc precursor, and hydrogen peroxide (H2O2) as the reactant. The ALD process of IZO deposition was carried by repeated supercycles, including one cycle of indium oxide (In2O3) and one cycle of zinc oxide (ZnO). The IZO growth rate deviates from the sum of the respective In2O3 and ZnO growth rates at ALD growth temperatures of 150, 175, and 200 °C. We propose growth temperature-dependent surface reactions during the In2O3 cycle that correspond with the growth-rate results. Thin-film transistors (TFTs) were fabricated with the ALD-grown IZO thin films as the active layer. The amorphous IZO TFTs exhibited high mobility of 42.1 cm2 V-1 s-1 and good positive bias temperature stress stability. Finally, flexible IZO TFT was successfully fabricated on a polyimide substrate without performance degradation, showing the great potential of ALD-grown TFTs for flexible display applications.